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| HANBit HMN12816D Non-Volatile SRAM MODULE 2Mbit (128K x 16-Bit), 40pin-Dip, 5V Part No. HMN12816D GENERAL DESCRIPTION The HMN12816D 128K x 16 nonvolatile SRAM's are 2,097,152-bit fully static, nonvolatile SRAM's, organized as 131,072 words by 16 bits. Each NVSRAM has a self contained lithium energy source and control circuitry which constantly monitors Vcc for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. DIP-package HMN12816D devices can be used in place of solutions which build nonvolatile 128Kx16 memory by utilizing a variety of discrete components. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. The HMN12816D uses extremely low standby current CMOS SRAM's, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EEPROM. FEATURES w Access time : 70, 85, 120, 150ns w High-density design : 256KByte Design w Battery internally isolated until power is applied w Industry-standard 40-pin 128K x 16 pinout w Unlimited write cycles w Data retention in the absence of VCC w 10-years minimum data retention in absence of power w Automatic write-protection during power-up/power-down cycles w Data is automatically protected during power loss w Conventional SRAM operation; unlimited write cycles PIN ASSIGNMENT /CEU /CEL DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 Vss DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 /OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc /WE A16 A15 A14 A13 A12 A11 A10 A9 Vss A8 A7 A6 A5 A4 A3 A2 A1 A0 OPTIONS w Timing 70 ns 85 ns 120 ns 150 ns MARKING - 70 - 85 -120 -150 40-pin Encapsulated Package URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 1 HANBit Electronics Co.,Ltd HANBit HMN12816D FUNCTIONAL DESCRIPTION The HMN12816D devices execute a read cycle whenever /WE (Write Enable) is inactive (high) and either/both of /CEU or /CEL (Chip Enables) are active (low) and /OE (Output Enable) is active (low). The unique address specified by the 17 address inputs (A0-A16) defines which of the 131,072 words of data is accessed. The status of /CEU and /CEL determines whether all or part of the addressed word is accessed. If /CEU is active with /CEL inactive, then only the upper byte of the addressed word is accessed. If /CEU is inactive with /CEL active, then only the lower byte of the addressed word is accessed. If both the /CEU and /CEL inputs are active (low), then the entire 16-bit word is accessed. Valid data will be available to the 16 data output drivers within tACC (Access Time) after the last address input signal is stable, providing that /CEU, /CEL and /OE access times are also satisfied. If /CEU, /CEL, and /OE access times are not satisfied, then data access must be measured from the later occurring signal, and the limiting parameter is either t CO for /CEU, /CEL, or tOE for /OE rather than address access. The HMN12816D devices execute a write cycle whenever /WE and either/both of /CEU or /CEL are active (low) after address inputs are stable. The unique address specified by the 17 address inputs (A0-A16) defines which of the 131,072 words of data is accessed. The status of /CEU and /CEL determines whether all or part of the addressed word is accessed. If /CEU is active with /CEL inactive, then only the upper byte of the addressed word is accessed. If /CEU is inactive with /CEL active, then only the lower byte of the addressed word is accessed. If both the /CEU and /CEL inputs are active (low), then the entire 16-bit word is accessed. The write cycle is terminated by the earlier rising edge of /CEU and/or /CEL, or WE. All address inputs must be kept valid throughout the write cycle. /WE must return to the high state for a minimum recovery time (tWR ) before another cycle can be initiated. The /OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled (/CEU and/or /CEL, and /OE active) then /WE will disable the outputs in tODW from its falling edge. PIN DESCRIPTION A0-A16 : Address Inputs /CEU : Chip enable upper byte /CEL : Chip enable lower byte DQ0-DQ15 : Data input / Data output /WE : Write enable /OE : Output enable VCC : +5V power supply Vss : Ground /CEL /CEU /OE /WE BLOCK DIAGRAM 2 x 128K x 8 SRAM Block Power /CEL A0-A16 DQ0-DQ15 /CEU Power - Fail Control Lithium Cell VCC URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 2 HANBit Electronics Co.,Ltd HANBit HMN12816D READ/WRITE FUNCTION CYCLE PERFORMED Output Disabled /OE H L L L X X X X /WE H H H H L L L X /CEL X L L H L L H H /CEU X L H L L H L H VCC CURRENT ICCO ICCO DQ0-DQ7 High-Z Output Output High-Z Input DQ8-DQ15 High-Z Output High-Z Output Input High-Z Input High-Z Read Cycle ICCO ICCS Input High-Z High-Z Write Cycle Output Disabled DATA RETENTION MODE The HMN12816D provides full functional capability for VCC greater than 4.5 volts and write protects by 4.25volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply volt-age decay, the NV SRAM's automatically write protect themselves, all inputs become "don't care," and all out-puts become high impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. ABSOLUTE MAXIMUM RATINGS PARAMETER DC voltage applied on VCC relative to VSS DC Voltage applied on any pin excluding VCC relative to VSS Operating temperature Storage temperature Temperature under bias Soldering temperature SYMBOL VCC VT TOPR TSTG TBIAS TSOLDER RATING -0.3V to 7.0V -0.3V to 7.0V 0 to 70C -40C to 70C -10C to 70C 260C For 10 second VT VCC+0.3 CONDITIONS NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 3 HANBit Electronics Co.,Ltd HANBit RECOMMENDED DC OPERATING CONDITIONS ( TA= TOPR ) PARAMETER Supply Voltage Ground Input high voltage Input low voltage SYMBOL VCC VSS VIH VIL MIN 4.5V 0 2.2 -0.3 TYPICAL 5.0V 0 - HMN12816D MAX 5.5V 0 Vcc+0.3V 0.8V NOTE: Typical values indicate operation at TA = 25 DC ELECTRICAL CHARACTERISTICS (TA= 0OC to 70 OC ) PARAMETER Input Leakage Current I/O Leakage Current CE VIHVCC Output Current @ 2.4V Output Current @0.4V Standby Current /CEU,/CEL=2.2V Standby Current /CEU,/CEL=Vcc-0.5V Operating Current ICCS2 ICCO1 SYMBOL IIL IIO IOH IOL ICCS1 MIN -2.0 -1.0 -1.0 2.0 TYP. 10 MAX +2.0 +1.0 20 UNIT mA mA mA mA mA - 6 10 170 mA mA CAPACITANCE (TA=25 , f=1MHz, VCC=5.0V) DESCRIPTION Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN TYP 20 5 MAX 25 10 UNITS pF pF URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 4 HANBit Electronics Co.,Ltd HANBit READ CYCLE (TA= TOPR, VCCmin VCC VCCmax ) PARAMETER Read Cycle Time Address Access Time Chip enable access time Output enable to Output valid Chip enable to output in low Z Output enable to output in low Z Chip disable to output in high Z Output disable to output high Z Output hold from address change SYMBOL tRC tACC tACE tOE tCLZ tOLZ tCHZ tOHZ tOH Output load A Output load A Output load A Output load B Output load B Output load B Output load B Output load A CONDITIONS -70 MIN 70 5 5 0 0 10 MAX 70 70 35 25 25 MIN 85 5 0 0 0 10 -85 MAX 85 85 45 35 25 -120 MIN 120 5 0 0 0 10 HMN12816D -150 MIN 150 10 5 0 0 10 MAX 150 150 70 60 50 - MAX 120 120 60 45 35 - UNIT ns ns ns ns ns ns ns ns ns WRITE CYCLE (TA= TOPR, Vccmin Vcc Vccmax ) PARAMETER Write Cycle Time Chip enable to end of write Address setup time Address valid to end of write Write pulse width Write recovery time (write cycle 1) Write recovery time (write cycle 2) Data valid to end of write Data hold time (write cycle 1) Data hold time (write cycle 2) Write enabled to output in high Z Output active from end of write SYMBOL tWC tCW tAS tAW tWP tWR1 tWR2 tDW tDH1 tDH2 tWZ tOW Note 4 Note 4 Note 5 Note 5 Note 1 Note 2 Note 1 Note 1 Note 3 Note 3 CONDITIONS -70 MIN 70 65 0 65 55 5 15 30 0 10 0 5 MAX 25 MIN 85 75 0 75 65 5 15 35 0 10 0 0 -85 MAX 30 -120 MIN 120 100 0 100 85 5 15 45 0 10 0 0 MAX 40 -150 Min 150 100 0 90 90 5 15 50 0 0 0 5 Max 50 UNI T ns ns ns ns ns ns ns ns ns ns ns ns NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high. 2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE going low and /WE going low. 3. Either tWR1 or tWR2 must be met. 4. Either tDH1 or tDH2 must be met. 5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in highimpedance state. URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 5 HANBit Electronics Co.,Ltd HANBit HMN12816D TIMING WAVEFORM READ CYCLE tRC Address tACC tCO /CEU, /CEL tOD /OE tOE DOUT tCOE Data Valid tOD tOH WRITE CYCLE NO.1 tWC Address tWR1 /CEU,/CEL tAW /WE tDS DIN tODW DOUT Data Undefined (1) Data-in Valid tOEW High-Z tDH1 tWP tWP URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 6 HANBit Electronics Co.,Ltd HANBit HMN12816D WRITE CYCLE NO.2 tWC Address tWR2 tWP /WE tAW /CEU,/CEL tDS DIN tCOE DOUT tODW High-Z Data-in Valid tDH2 tWP POWER-DOWN/POWER-UP CONDITION VCC VTP 3.2V tF tPD /CEU,/CEL tR tREC Data Retention Time TDR URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 7 HANBit Electronics Co.,Ltd HANBit POWER-DOWN/POWER-UP TIMING(tA= 0OC to 70OC) PARAMETER /CEU,/CEL at VIH before Power-Down VCC Slew from VTP to 0V VCC Slew from 0V to VTP /CEU,/CEL at VIH after Power-Up SYMBOL tPD tF tR tREC MIN 0 300 300 2 TYP. MAX 125 HMN12816D UNITS us us us us NOTES 11 - (tA= 25 C) PARAMETER Expected Data Retention Time WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES 9 O NOTES: 1. /WE is high for a read cycle. 2. /OE = VIH or VIL . If /OE = VIH during write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical and of /CEU or /CEL and /WE. tWP is measured from the latter of /CEU, /CEL or /WE going low to the earlier of /CEU, /CEL or /WE going high. 4. tDS is measured from the earlier of /CEU or /CEL or /WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the /CEU or /CEL low transition occurs simultaneously with or later than the /WE low transition in the output buffers remain in a high impedance state during this period. 7. If the /CEU or /CEL high transition occurs prior to or simultaneously with the /WE high transition, the output buffers remain in high impedance state during this period. 8. If /WE is low or the /WE low transition occurs prior to or simultaneously with the /CEU or /CEL low transition, the output buffers remain in a high impedance state during this period. 9. Each HMN12816D has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. 10. All AC and DC electrical characteristics are valid over the full operating temperature range 0_C to 70_C. 11. In a power down condition the voltage on any pin may not exceed the voltage on Vcc . 12. tWR1, tDH1 are measured from /WE going high. 13. tWR2, tDH2 are measured from /CEU or /CEL going high. URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 8 HANBit Electronics Co.,Ltd HANBit HMN12816D PACKAGE DIMENSION Dimension A B C D E F G H I J Min 2.070 0.710 0.365 0.015 0.008 0.590 0.017 0.090 0.080 0.120 Max 2.100 0.740 0.375 0.013 0.630 0.023 0.110 0.110 0.150 J A I H G C D B E F All dimensions are in inches. ODERING INFORMATION H M N 128 16 D - 70 I Operating Temp. : Blank = Commercial (0 to 70 C ) I = Industrial (-40 to 85C) Speed options : 70 = 70 ns 85 = 85 ns Dip type package Device : 128K x 16 bit Nonvolatile SRAM HANBit Memory Module 120 = 120 ns 150 = 150 ns URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 9 HANBit Electronics Co.,Ltd |
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